1. Field of the Invention
The present invention relates to a frame synchronization method and a frame synchronization circuit which are applicable to ATM (Asynchronous Transfer Mode) communications, especially an ATM physical layer protocol.
2. Description of the Prior Art
Data transmission processes for ATM communications include a process for storing ATM cells in transmission frames according to SDH (Synchronous Digital Hierarchy) and transmitting the stored ATM cells, and a process for transmitting ATM cells per se on a transmission path. Frame synchronization according to the former transmission process will be described below by way of example.
An STS (Synchronous Transport Signal)-N frame structure for an ATM physical layer interface is illustrated in FIG. 1 of the accompanying drawings. The STS-N frame has Nxc3x9790 bytesxc3x979 columns, and comprises two areas, i.e., a transport overhead of 3xc3x97N bytes and an STS-N envelope capacity storing ATM cells therein. xe2x80x9cNxe2x80x9d in the STS-N frame represents a multiplex level.
Frame synchronization patterns A1, A2 indicating the beginning of the frame are set in the transport overhead in the first column of the STS-N frame. Each of the frame synchronization patterns A1, A2 comprises N bytes. If the frame synchronization pattern A1 is set to xe2x80x9cF6xe2x80x9d and the frame synchronization pattern A2 is set to xe2x80x9c28xe2x80x9d, for example, then a frame synchronization pattern F628[HEX: hexadecimal notation] is established.
FIG. 2 of the accompanying drawings shows frame synchronization state transitions according to a conventional frame synchronization method. A state for establishing synchronization from an out-of-synchronization state is referred to as a HUNT state. In the HUNT state, a received STS-N frame is inspected to ascertain whether the frame synchronization pattern F628[HEX] is detected or not. If the frame synchronization pattern F628[HEX] is detected once from the received STS-N frame, then it is assumed that the beginning of the frame is detected, and a transition occurs from the HUNT state to a PRESYNC state (pre-synchronization state). If the frame synchronization pattern F628[HEX] is not detected, a successively received STS-N frame is inspected.
In the PRESYNC state, a STS-N frame received after the STS-N frame from which the frame synchronization pattern F628[HEX] has been detected in the HUNT state is inspected to ascertain whether the frame synchronization pattern F628[HEX] is consecutively detected at the A1, A2 byte positions. If the frame synchronization pattern F628[HEX] is consecutively detected at the A1, A2 byte positions, then a transition occurs from the PRESYNC state to a SYNC state (synchronization state). If the frame synchronization pattern F628[HEX] is not detected, then a transition occurs from the PRESYNC state back to the HUNT state.
In the SYNC state, a received STS-N frame is inspected to ascertain whether the frame synchronization pattern F628[HEX] is detected or not. If the frame synchronization pattern F628[HEX] is not detected at the A1, A2 byte positions., then a transition occurs from the SYNC state to a PREHUNT state (pre-hunting state). If the frame synchronization pattern F628[HEX] is detected at the A1, A2 byte positions, then a successively received STS-N frame is inspected.
In the PREHUNT state, it is inspected whether the frame synchronization pattern F628[HEX] is detected in three consecutive frames at the A1, A2 byte positions or not. If the frame synchronization pattern F628[HEX] is not detected in three consecutive frames, then a transition occurs from the PREHUNT state to the HUNT state. If the frame synchronization pattern F628[HEX] is detected even once, a transition occurs from the PREHUNT state back to the SYNC state (synchronization state).
In the above frame synchronization, it is necessary that the frame synchronization pattern F628[HEX] be detected consecutively twice as a condition to be met in order to enter the SYNC state from the HUNT state via the PRESYNC state, and it is necessary that the frame synchronization pattern F628[HEX] be not detected consecutively four times as a condition to be met in order to enter the HUNT state from the SYNC state via the PREHUNT state. Such conditions for determining synchronization and out-of-synchronization are referred to as backward protection and forward protection, respectively, and the numbers of conditions to be met are referred to as backward protection stage count xcex4 and forward protection stage count xcex1, respectively. In the above conventional frame synchronization, the backward protection stage count xcex4=2 and the forward protection stage count xcex1=4.
If the forward protection stage count xcex1 is reduced, then the danger of an erroneous transition to the HUNT state due to a transmission error is increased. If the forward protection stage count xcex1 is increased, then the time consumed after synchronization until the HUNT state is reached is increased. If the backward protection stage count xcex4 is reduced, then the danger of an erroneous detection of a frame synchronization pattern is increased. If the backward protection stage count xcex4 is increased, then the probability of a return to the HUNT state is increased.
It is preferable that the user be allowed to set the backward protection stage count xcex4 and the forward protection stage count xcex1 to arbitrary values in view of their characteristics described above. Heretofore, however, the backward protection stage count xcex4 and the forward protection stage count xcex1 are fixed to xcex4=2, xcex1=4, and the user is unable to set these counts to arbitrary values. If transitions from the HUNT state via the PRESYNC state to the SYNC state and then from the SYNC state via the PREHUNT state to the HUNT-state are carried out in actual operation, 6 frames (125 xcexcsec.xc3x976 frames=750 xcexcsec.) are required at a minimum, and the user cannot shorten this period of time.
Japanese laid-open patent publication No. 8-214002 discloses a frame synchronization process which has one forward protection stage and one backward protection stage for frame synchronization with respect to an EMSD (Extended Maintenance Signal Driver) highway. According the disclosed frame synchronization process, if a normal synchronization FCK is received in the hunting state, data start to be read from a corresponding frame. If an abnormal synchronization FCK is received even once in the synchronization state, then a transition occurs from the synchronization state to the hunting state. Data from that time on are discarded, and the data received immediately prior to that time is maintained until synchronization is established next time. According the disclosed frame synchronization process, however, the user is unable to set the backward protection stage count xcex4 and the forward protection stage count xcex1 to arbitrary values.
It is therefore an object of the present invention to provide a frame synchronization method and a frame synchronization circuit which allow the user to set the backward protection stage count xcex4 and the forward protection stage count xcex1 to arbitrary values.
To achieve the above object, there is provided in accordance with the present invention a method of achieving frame synchronization for received frame data with a predetermined frame synchronization pattern inserted in the beginning of each of transmission frames containing ATM cells in a frame synchronization circuit, comprising the steps of detecting the frame synchronization pattern from the received frame data, generating a first pulse signal of one clock pulse in timed relationship to the detection of the frame synchronization pattern from the received frame data, detecting a transition from a hunting state to one of pre-synchronization state, a synchronization state, and a pre-hunting state for frame synchronization of the frame synchronization circuit, generating a second pulse signal in a period corresponding to a frame period of the received frame data in timed relationship to the detection of the transition, managing the number of times that the frame synchronization pattern is detected and the number of times that the frame synchronization pattern is not detected, based on the first pulse signal and the second pulse signal, making a transition from the hunting state to the synchronization state if the frame synchronization pattern is detected consecutively for a backward protection stage count which is voluntarily set up as a protection condition to be met in order to change from the hunting state to the synchronization state, and making a transition from the synchronization state to the hunting state if the frame synchronization pattern is not detected consecutively for a forward protection stage count which is voluntarily set up as a protection condition to be met in order to change from the synchronization state to the hunting state.
According to the present invention, there is also provided a frame synchronization circuit for achieving frame synchronization for received frame data with a predetermined frame synchronization pattern inserted in the beginning of each of transmission frames containing ATM cells, comprising frame synchronization pattern detecting means for detecting the frame synchronization pattern from the received frame data and generating a first pulse signal of one clock pulse in timed relationship to the detection of the frame synchronization pattern from the received frame data, frame synchronization state transition managing means for managing frame synchronization state transitions, and frame timing generating means for detecting a transition from a hunting state to another state for frame synchronization, and generating a second pulse signal in a period corresponding to a frame period of the received frame data in timed relationship to the detection of the transition, the frame synchronization state transition managing means comprising means for managing the number of times that the frame synchronization pattern is detected and the number of times that the frame synchronization pattern is not detected, based on the first pulse signal and the second pulse signal, and making a transition from the hunting state to a synchronization state if the frame synchronization pattern is detected consecutively for a backward protection stage count which is voluntarily set up as a protection condition to be met in order to change from the hunting state to the synchronization state, and making a transition from the synchronization state to the hunting state if the frame synchronization pattern is not detected consecutively for a forward protection stage count which is voluntarily set up as a protection condition to be met in order to change from the synchronization state to the hunting state.
With the arrangement of the present invention, certain conditions need to be met for a transition from the hunting state to the synchronization state and a transition from the synchronization state to the hunting state depending on the backward protection stage count and the forward protection stage count. The backward protection stage count and the forward protection stage count can be set to arbitrary values by the user. For example, the user can set each of the backward protection stage count and the forward protection stage count to xe2x80x9c1xe2x80x9d. The period of time required in actual operation to effect a transition from the hunting state via the pre-synchronization state to the synchronization state and from the synchronization state via the pre-hunting state to the hunting state may be 2 frames (125 xcexcsec.xc3x972 frames=250 xcexcsec.). Since the same period of time has heretofore been 6 frames, the period of time is reduced to one-third according to the present invention. Because four frames are eliminated, an amount of data represented by 48xc3x9790xc3x979 (bytes/frame)xc3x974 frames=155,520 (bytes) can be eliminated at a maximum (STM-16 for SDH and OC-48 for SONET).
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.